1. Field of the Invention
The present invention relates to a logic circuit, or more particularly, to a logic circuit acting as a flip-flop circuit with a data-selecting function.
2. Description of the Related Art
For constructing a logic circuit that acts at a high speed, it is generally known to adopt a pipeline structure. The pipeline structure is such that: flip-flops are included in an combinational circuit; the combinational circuit is divided into a plurality of stages segmented with the flip-flops; and the stages are worked simultaneously in order to carry out processing. Adoption of the pipeline structure improves a throughput and speeds up the action of the whole logic circuit. Thus, the flip-flops serve as basic circuits required for realizing a logic circuit.
FIG. 2 shows an example of a flip-flop circuit employed conventionally. The flip-flop circuit consists of five inverters IV1 to IV5, two tristate inverters TIV1 and TIV2, and two transmission gates TG1 and TG2. The flip-flop circuit inputs a voltage of an input signal I1 developed with the rising of a clock signal CLK that is a reference signal based on which the circuit acts. The flip-flop circuit then outputs the signal through an output port O1 and retains the state thereof until the next rising of the clock signal CLK. FIG. 3 is a truth table indicating the action of the flip-flop circuit shown in FIG. 2.
When the flip-flop circuit shown in FIG. 2 is actually produced, it causes a propagation delay as indicated in the timing chart of FIG. 4. Therefore, a signal is developed at the output port O1 in a certain time (delay time td) after the rising of the clock signal CLK. Moreover, circuit elements causing a propagation delay are interposed between the input port I1 and a node n1 at which data is stored. For this reason, a signal to be applied to the input port I1 must be produced by a time, which is longer than the certain time (setup time ts), earlier than the rising of the clock signal CLK.
FIG. 5 shows an example of a pipeline circuit having a combinational circuit Comb interposed between flip-flop circuits F/F. In the pipeline circuit, a cycle time tcyc is determined with the sum of a delay time caused by the flip-flop circuits themselves (a delay time td plus a setup time ts) and a delay time occurring between the flip-flop circuits (that is, a delay time tcomb caused by the combinational circuit). Whether the delay times can be reduced as much as possible has a significant meaning in designing a pipeline circuit that acts at a high speed. The cycle time tcyc required by the pipeline circuit is expressed as follows: EQU tcyc=ts+td+tcomb (1)
For allowing a logic circuit to act at a high speed, the cycle time tcyc must be reduced. However, the combinational circuit Comb cannot be excluded in order to realize a large-scale integration (LSI) having an intended logic function. Moreover, a delay time caused by one circuit element is shorter than that caused by a flip-flop circuit F/F. Therefore, realizing a flip-clop circuit that acts at a high speed is essential to an increase in the speed at which a logic circuit acts.
Circuitry having a flip-flop circuit that includes a circuit element for realizing an added function is known as a means for speeding up the action of a logic circuit using a flip-flop circuit. The circuit has been disclosed in, for example, Japanese Unexamined Patent Publication Nos. 7-231246 and 6-45879.
The Japanese Unexamined Patent Publication No. 7-231246 describes circuitry having a latch circuit, which is a component of a flip-flop circuit, with a NAND function. When the latch circuit having the NAND function is used to construct a flip-flop circuit, an NAND element is substituted for the inverter IV3 or IV5 in the flip-flop circuit shown in FIG. 2. The substitution realizes a flip-flop circuit having the NAND function.
Moreover, the Japanese Unexamined Patent Publication No. 6-45879 describes circuitry having a flip-flop circuit with a data-selecting function. The circuitry is concerned with a flip-flop circuit having a master/slave structure. The flip-flop circuit with a data-selecting function is realized by adding to a master stage a feature for latching a plurality of data items and a feature for selecting one data from the data items and transferring the selected data to a slave stage.
However, in the flip-flop circuit with a data-selecting function disclosed in the Japanese Unexamined Patent Publication No. 6-45879, three circuits must be included for holding data. This leads to a large area. Besides, the number of selectable data items is two.